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A design layout record (DLR) or circuit layout record (CLR) is used in the telecommunication industry to describe the detailed design path of a completed circuit, including all equipment and network components from one end of the circuit to the other. It may be detailed enough to include location, floor, row, rack, panel and port for each circuit component or it may simply refer to another previously engineered circuit. A DLR may describe an end-to-end circuit that comprises physical or virtual circuits. As an example, a physical facility would include a panel, rack and port, while a virtual facility may be a channel on a channelized circuit, such as a T1 on a previously engineered DS3. ==Explanation== There are two parts to a circuit: # Physical design/path # Logical design/path The design team is responsible to find the best, lowest-cost path for the circuit being designed, and get the physical line provisioned. When their role is complete, the order is passed to another team who take care of establishing logical design and accessibility of the circuit. Every network element that is part of the circuit needs to be built and checked. The DLR provides a systematic way to identify the network elements and their attributes. With the aid of the DLR, a team installs the circuit and tests it to check that it meets the customer's specifications. There are many ways to prepare a DLR. Many include: * Network elements, port and channel assignment * Cross connects: hard and soft * Rings * Location codes for sites where equipment is housed * IP address, slots for network elements and other fine details as such 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Design layout record」の詳細全文を読む スポンサード リンク
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